Because they are programmable, FPGAs can be configured (i.e., programmed) to support different signal and data processing applications. In order to expand the number of different types of applications that an FPGA can support, conventional FPGAs are typically designed with an I/O buffer architecture that supports different signaling protocols, including both single-ended and differential signaling protocols.
One way to provide an FPGA that supports a variety of different signaling protocols is to implement the FPGA with programmable I/O buffers, where each programmable I/O buffer supports any and all of the desired signaling protocols. While such an approach provides an FPGA with a high level of functional flexibility, it does so at the cost of having to implement individual, all-purpose I/O buffers that are relatively large (in layout area).
Some prior-art FPGAs have single-ended I/O buffers with PCI (Peripheral Component Interconnect) clamps and single-ended I/O buffers without PCI clamps. While these FPGAs may support 3.3V signaling on all four sides of the devices and adequate PCI support, they do not provide LVDS (Low-Voltage Differential Signaling) support.
Other prior-art FPGAs have single-ended and differential buffers with PCI clamps. While these FPGAs may provide adequate PCI and LVDS support, they do not support 3.3V Series Stub Terminated Logic (SSTL3) signaling on all four sides of the devices.